Makefile command

Suppose, hypothetically, I have a program "foo" which produces either or both of "apple.out" or "berry.out" from "apple.in" and "berry.in", and I wish to include an instruction in a makefile something like:

apple.out berry.out : apple.in berry.in
    foo apple.foo berry.foo

However, there's significant processing involved in running foo at all, and also in using an additional input file, so we wish to invoke foo once, with only the command line options necessary.

Is there any way to do so with a makefile?

I thoguht of two ways. Firstly, using conditionals and text-processing in the makefile to scan the targets requested on the command line, and if both "apple.out" and "berry.out" are requested, replace them with a phony target, something like "both.out", and then have separate rules for each of three possible targets. But does that work if one of the output files is not requested, but is a dependency of something else?

Secondly, using a temporary files to request invocation of "foo", say have a phony dependency of "apple.out" that creates a file "wantapple", and then a little fiddling to invoke "foo" with the names of those temporary "want" files, and then delete them. And an order-only dependency to ensure the temporary files are created before "foo" is invoked (if it is invoked at all).

But neither solution is at all elegant. Is there an approved way of doing so? Or is the approved way to stop being stubborn and use a program rather than make to do the decision making? A quick bit of research online produced no definitive answers, though several people asked about programs which always produced both outputs.

Edit: Yes, I wasted too long wondering about this when I ought to have just ignored it, rebuilt both every time, and got on with things :)